Technical Specifications for the BeBox
BeBox Main Processor Board
The processor board is a 6-layer printed circuit board (PCB) with components
mounted only on the top surface. Integrated circuits and passives are
surface-mounted, connectors are through-hole. The processors are soldered
directly to the processor board.
Over the lifetime of the BeBox, 8 different revisions of the BeBox mainboard
were developed. [More information]
Diagram of the BeBox Main Processor Board
Photo of the BeBox Main Processor Board
Main Processor Board Components and Connectors
Qty
|
Component
|
Connector
|
| 2
|
PowerPC 603 or 603e RISC processors at 66 or 133 Mhz
|
|
| 8
|
72-bit DRAM SIMM Sockets
|
72-pin
|
| 1
|
8-bit flash ROM
|
|
| 3
|
32-bit PCI slots at 33 MHz
|
32-bit PCI
|
| 5
|
16-bit ISA slots
|
16-bit ISA
|
| 1
|
Real-time clock with battery-backed-up NVRAM
|
|
| 1
|
Internal SCSI port
|
50-pin ribbon
|
| 1
|
External SCSI port
|
50-pin SCSI II
|
| 1
|
Parallel port
|
25-pin D-shell
|
| 1
|
Internal ATA (IDE) port
|
40-pin ribbon
|
| 1
|
Keyboard port, PC/AT-type
|
5-pin DIN
|
| 1
|
Internal floppy port
|
34-pin ribbon
|
| 1
|
Speaker port
|
2-pin
|
| 1
|
Front panel connector
|
26-pin ribbon
|
| 1
|
Power LED
|
|
| 1
|
Disk-activity LED
|
|
| 1
|
Interrupt switch
|
|
| 1
|
Reset switch
|
|
| 1
|
Bar-graph LED driver
|
|
BeOS Kernel Source Code
For those interested, below is the joe.h header file from the BeOS
Kernel. It contains definitions required by the BeOS source code for the
BeBox.
/* ++++++++++
$Source: /net/bally/be/rcs/src/nukernel/arch/joe/joe.h,v $
$Revision: 1.1 $
$Author: cyril $
$Date: 1996/11/05 00:50:24 $
Copyright (c) 1994 by Be Incorporated. All Rights Reserved.
Definitions specific to the 'Joe' motherboard
+++++ */
#ifndef _JOE_H
#define _JOE_H
#ifndef _EAGLE_H
#include
#endif
/* ---
define this to enable the Intel 82378 DMA fix
--- */
#define FLUSH_INTEL
/* ---
motherboard-specific definitions
--- */
#define CLOCK_SPEED_HZ 33238632
#define MAX_CPU 2
#define RAM (HOST_LOCAL_MEMORY)
#define CPU_0_ID 0
#define CPU_1_ID 1
#define CPU_ID_LOW CPU_0_ID
#define CPU_ID_HIGH CPU_1_ID
/* ---
glue logic registers for interrupt/reset control
--- */
#define MOTHERBOARD_IO 0x7ffff000 /* base address of motherboard regs */
#define CPU0_INT_MASK 0x0f0 /* interrupt mask for cpu 0 */
#define CPU1_INT_MASK 0x1f0 /* interrupt mask for cpu 1 */
#define INT_SOURCE 0x2f0 /* interrupt source */
#define CPU_CONTROL 0x3f0 /* inter-cpu interrupts, tlbisyncs */
#define CPU_RESET 0x4f0 /* CPU 1, 486 card reset control */
/* masks for controlling cpus */
#define CPU0_SMI 0x40000000 /* bit for SMI to cpu 0 */
#define CPU1_SMI 0x20000000 /* bit for SMI to cpu 1 */
#define CPU1_INT 0x10000000 /* bit for INT to cpu 1 (rev1 motherboard only) */
#define CPU0_TLBISYNC 0x08000000 /* bit for tlbisync to cpu 0 */
#define CPU1_TLBISYNC 0x04000000 /* bit for tlbisync to cpu 1 */
#define WHO_AM_I 0x02000000 /* 1 if cpu 1, 0 if cpu 0 */
/* masks for resetting cpus, other stuff */
#define CPU1_SRESET 0x40000000 /* bit for SRESET to cpu 1 */
#define CPU1_HRESET 0x20000000 /* bit for HRESET to cpu 1 */
#define SIO82378_FIX 0x10000000 /* fix Intel SIO 82378 (see below) */
#define X86_HRESET 0x01000000 /* hard reset of x86 card */
/* ---
The Intel SIO 82378 has a bug where DREQ's may not get recognized. The
workaround is to connect FLUSHREQ# to MEMACK# instead of to the
corresponding pins on the Eagle (MPC105). Unfortunately this breaks
interrupt acknowledge cycles, so we temporarily reconnect them to Eagle
for int-acks. Hence this bit.
--- */
/* handy stuff for getting at i/o interrupt status */
#define IMPLEMENTED_MASK 0x6FFFFFFC /* all bits in INT_SOURCE */
#define INT_SOURCE_MASK 0x0FFFFFFC /* meaningful i/o bits in INT_SOURCE */
#define INT_TO_MASK(IO_INT_NUMBER) (1<<(31-(IO_INT_NUMBER)))
/* interrupt numbers for the various interrupt sources. These correspond
to bit positions in the interrupt mask and status registers */
#define JOE_INT_LOW 4
#define JOE_INT_IRQ4 4
#define JOE_INT_COM1 (JOE_INT_IRQ4)
#define JOE_INT_IRQ3 5
#define JOE_INT_COM2 (JOE_INT_IRQ3)
#define JOE_INT_SERIAL3 6
#define JOE_INT_SERIAL4 7
#define JOE_INT_MIDI1 8
#define JOE_INT_MIDI2 9
#define JOE_INT_SCSI 10
#define JOE_INT_PCI1 11
#define JOE_INT_PCI2 12
#define JOE_INT_PCI3 13
#define JOE_INT_SND 14
#define JOE_INT_IRQ1 15
#define JOE_INT_KBD (JOE_INT_IRQ1)
#define JOE_INT_IRQ8 16
#define JOE_INT_RTC (JOE_INT_IRQ8)
#define JOE_INT_IRQ5 17
#define JOE_INT_IRQ6 18
#define JOE_INT_FDC (JOE_INT_IRQ6)
#define JOE_INT_IRQ7 19
#define JOE_INT_LPT (JOE_INT_IRQ7)
#define JOE_INT_IRQ9 20
#define JOE_INT_IRQ10 21
#define JOE_INT_IRQ11 22
#define JOE_INT_IRQ12 23
#define JOE_INT_MOUSE (JOE_INT_IRQ12)
#define JOE_INT_IRQ14 24
#define JOE_INT_IRQ15 25
#define JOE_INT_8259 26
#define JOE_INT_IR 27
#define JOE_INT_A2D 28
#define JOE_INT_GEEK 29
#define JOE_INT_HIGH 29
#define JOE_INT_UNUSED 30
/* pci device IDs of onboard pci devices */
#define MPC105_PCI_ID 0
#define INTEL82378_PCI_ID 11
#define NCR53C810_PCI_ID 12
#endif
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