Technical Specifications for the BeBox
Memory Controller and PCI Bridge
The MPC105 chip performs the following
functions:
- DRAM The memory controller supports up to 8 banks
of RAM in 4 socket pairs. RAM SIMMs must be added in pairs to make up the
64-bit data path. Parity is not checked in the initial release of the BeBox
software, but parity checking will be an option in future releases. Parity
SIMMs (36-bit) or nonparity SIMMs (32-bit) may be used. The RAM SIMMs should
be 60 nS or faster, fast page mode. SIMMs of 1, 2, 4, 8, 16, 32, and 128
MB size are supported.
- FLASH ROM The memory controller assembles bytes from
the flash ROM into 32-bit words for the processor. A single flash ROM of
128 K bytes is provided. The first sector of the ROM is write-protected
and contains code for updating or repair of the rest of the ROM from a
floppy disk.
- PCI Bridge The PCI bridge performs processor-to-PCI
and PCI-to-memory system transactions. Access to the memory system from
PCI are snooped by the processors to maintain cache coherency. Endian
conversion
is performed for transactions between PCI and the processor bus.
- Processor Bus Arbitration The 105 provides arbitration
for the processor bus. Each processor and PCI may arbitrate for the bus.
Further Memory Controller/PCI Bridge Information
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