Technical Specifications for the BeBox
Reset and Interrupts
Reset and interrupts are supported via two FPGAs. These chips perform the
following functions:
- Reset Counter Provides reset pulse to the processors.
- Bus interface Connects CPU bus to interrupt registers,
supports split transaction bus.
- Interrupts - Inter-processor Provides communication
between processors
- Interrupts - I/O Each processor has a interrupt mask
register to permit each of the interrupts to be individually masked to
each processor.
Reset and interrupt are available as front panel switches. The left and
right switches work in combination to provide the following functions:
Left Right Function
---- ----- -------------------------------------------------
N N Normal operating condition
Y N Interrupt pressed, system interrupts to debugger
N Y Reset pressed, no effect (safe to press either button)
Y Y System hard reset. Contents of RAM will be lost.
Interrupt Source Code
Below are some choice selections from the BeOS kernel that relate to BeBox
Interrupts:
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